1. Field of the Invention
The present invention is related to a capacitance compensation circuit of an RF (radio frequency) switch, and more particularly, to a capacitance compensation circuit which improves voltage distribution of the RF switch.
2. Description of the Prior Art
Please refer to FIG. 1 and FIG. 2. FIG. 1 is a diagram illustrating a prior art RF switch 100. The RF switch 100 includes a transistor 102 having a first parasitic capacitor Cgd coupled between a gate and a drain of the transistor 102, a second parasitic capacitor Cgs coupled between the gate and a source of the transistor 102, a third parasitic capacitor Cdb coupled between a well and the drain of the transistor 102, and a fourth parasitic capacitor Csb coupled between the well and the source of the transistor 102.
FIG. 2 is a timing diagram illustrating voltage signals on the prior art RF switch 100 when the RF switch 100 is turned off. In FIG. 2, −VR_DC is a DC (direct current) voltage difference between the source and the drain of the transistor 102, BVdss is source-to-drain breakdown voltage of the transistor 102, Vth is threshold voltage of the transistor 102, Vgs is a voltage difference between the gate and the source of the transistor 102 illustrated by a solid line, and Vgd is a voltage difference between the gate and the drain of the transistor 102 illustrated by a dashed line. Vgs and Vgd are AC signals superimposed on the DC value (−VR_DC), swinging positively or negatively.
FIG. 2 illustrates an ideal condition where capacitance of the first parasitic capacitor Cgd is equal to capacitance of the second parasitic capacitor Cgs when the RF switch 100 is turned off. Thus, impedance between the gate and the source of the transistor 102 is equal to impedance between the gate and the drain of the transistor 102, and voltage amplitude of an RF signal across the source and the drain of the transistor 102 is distributed evenly to Vgs and Vgd. That is, voltage amplitude of Vgs at time point A of FIG. 2 is equal to voltage of Vgd at time point B of FIG. 2. For example, supposing −VR_DC is −3V and voltage amplitude between the source and the drain of the transistor 102 is ±3V, if the voltage amplitude between the source and the drain of the transistor 102 is evenly distributed to Vgs and Vgd, the voltage amplitude of Vgs will be ±1.5V and the voltage amplitude Vgd will also be ±1.5V. Besides, a phase difference of 180 degrees exists between Vgs and Vgd. Thus the voltage of Vgs is −1.5V and the voltage of Vgd is −4.5V at time point A of FIG. 2, and the voltage of Vgs is −4.5V and the voltage of Vgd is −1.5V at time point B of FIG. 2. As long as the voltage amplitudes of both Vgs and Vgd are smaller than Vth or BVdss, the transistor 102 remains turned off.
However, in the real world, the capacitance of the first parasitic capacitor Cgd is related to bias voltage between the gate and the drain of the transistor 102 and the capacitance of the second parasitic capacitor Cgs is related to bias voltage between the gate and the source of the transistor 102. For example, the bias voltage between the gate and the drain of the transistor 102 is −4.5V and the bias voltage between the gate and the source of the transistor 102 is −1.5V at time point A of FIG. 2, thus the capacitance of the first parasitic capacitor Cgd is different from the capacitance of the second parasitic capacitor Cgs. In addition, the distributions of the voltage amplitude of Vgd and Vgs are inversely proportional to the capacitance of the first parasitic capacitor Cgd and the capacitance of the second parasitic capacitor Cgs respectively. As a result, the voltage amplitude between the source and the drain of the transistor 102 is distributed according to a capacitance ratio of Cgd to Cgs, unlike in the ideal condition. If the capacitance ratio of Cgd to Cgs is too big or too small, the voltage amplitude of either Vgs or Vgd may be bigger than Vth or BVdss, which may cause the transistor 102 to turn on falsely.
The third parasitic capacitor Cdb and the fourth parasitic capacitor Csb apply the same aforementioned principles. Under ideal conditions, capacitance of the third parasitic capacitor Cdb is equal to capacitance of the fourth parasitic capacitor Csb of the transistor 102, thus impedance between the well and the source of the transistor 102 is equal to impedance between the well and the drain of the transistor 102, and the voltage amplitude between the source and the drain of the transistor 102 is distributed evenly to Vdb and Vsb, wherein Vdb is a voltage difference between the well and the drain of the transistor 102 and Vsb is a voltage difference between the well and the source of the transistor 102. However, in the real world, the capacitance of the third parasitic capacitor Cdb is different from the capacitance of the fourth parasitic capacitor Csb, thus the voltage amplitude between the source and the drain of the transistor 102 is distributed unevenly to Vdb and Vsb. If the capacitance ratio of Cdb to Csb is too big or too small, Vdb or Vsb may be bigger than Vth or BVdss, the transistor 102 will also be turned on falsely.